Velox Intelligence · Hangzhou VXI Technology
Purpose-Built Brain
for Edge AI Deployment
VXI 22nm SRAM-CIM × 1.5B LLM @ 5W → 35-45 tok/s
Mesh NoC + 64 MB CIM + 32 MB on-chip KV = The physics solution to memory-bound crisis
Market Pain Points
Three Bottlenecks of On-Device LLM
In 2024-2026, the on-device wave of DeepSeek, Qwen, Llama rewrites the rules: the bottleneck shifts from 'insufficient compute' to 'insufficient memory bandwidth'.
Bandwidth Saturation
Under LPDDR5's 25.6 GB/s physical ceiling, 1.5B model decode theoretically maxes at 33 tok/s, real-world often drops to 5-8 tok/s.
30x Efficiency Collapse
Traditional NPUs claim 30 TOPS/W, but in LLM scenarios, after deducting LPDDR data movement power, it collapses to < 0.5 TOPS/W.
5W Thermal Barrier
System power surges to 10-15W, making fanless enclosures, robot dogs, and palm-sized private cloud devices impossible to deploy.
Solution
The Physics Solution to Memory-Bound Crisis
Mesh NoC + 64 MB CIM + 32 MB on-chip KV
System-Level Efficiency
27.8 TOPS/W
128 CIM Tiles × 512 KB
64 MB CIM array, weight-stationary + in-situ MAC, on-chip interconnect TB/s bandwidth
Mesh NoC 2 GHz, 256-bit
Unidirectional 64 GB/s cross-tile bandwidth, far exceeding LPDDR5's 25.6 GB/s ceiling
32 MB High-Density SRAM
16 MB KV Cache + 8 MB Activation Buffer + 8 MB Scratchpad, 8K context on-chip
0
CIM Tiles
0 MB
CIM Capacity
0 W
True Embedded TDP
0 tok/s
1.5B Decode Rate
Product Matrix
Four Domain SKUs, One Master SoC
Derived from a single master SoC through CIM tile count, SRAM capacity, security modules, and interface combinations.
Applications
From Personal Cloud to Edge Server
Personal Private Cloud / Me-Box
5W passive cooling + 1.5B fluent conversation + Web3 identity signing, data never leaves the shell.
Explore Scenarios
Xinchuang Desktop / Workstation
22nm domestic production, autonomous & controllable, SM4 hardware encryption, DeepSeek 7B becomes desktop standard.
Explore Scenarios
Industrial / Robot Dog Brain
Wide-temp fanless, real-time inference + VLA vision-language-action model, the core brain of embodied intelligence.
Explore ScenariosProduct Roadmap
Tape-out Status & Milestones
2026 Q4
Master SoC Tape-out
2027 Q2
ASIC Bring-up
2027 Q4
VXI-EM5/XC8 Mass Production
2028 Q1
VXI-IR5 Mass Production
Specifications on this page are pre-silicon design targets. VXI 22nm SRAM-CIM ASIC is planned for Q4 2026 tape-out / Q2 2027 bring-up.
Ready to Start Evaluation?
VXI8805 FPGA evaluation board is now available, bundled with SDK + pre-quantized model packages for immediate software stack validation and model PoC.